Prior designs for a CMOS to ECL output buffer, which were designed to have an output voltage swing meeting 100 k ECL specifications and which maintained a termination voltage between ECL V.sub.OH and V.sub.OL have been found to dissipate 200 milliwatts for single-ended designs. These designs also use off-chip components to provide reference signals to the output buffers.
Thus, a need exists for an efficient high-speed CMOS to ECL line driver which can be fully integrated on a single chip.